1. Field of the Invention
This invention relates to Schmitt trigger circuits, and more particularly to Schmitt triggers in which separate bias circuits are provided for setting the Schmitt's switching voltage levels.
2. Description of the Prior Art
A Schmitt trigger circuit functions as a level-detecting comparator with hysteresis. Its output changes from a LO to a HI state when an increasing input signal crosses an upper switching threshold Vhi, and reverts back to its initial state only when the input crosses a lower threshold level Vlo which is less than Vhi. The difference between the two threshold levels, Vhi-Vlo, is the hysteresis associated with the switch. Schmitt trigger circuits are commonly used in applications such as R-C relaxation oscillators; several different designs are described for example in Grebene, Bipolar and MOS Analog Integrated Circuit Design, John Wiley & sons, 1984, pages 556-564.
A typical input-output voltage characteristic for a non-inverting Schmitt trigger circuit is illustrated in FIG. 1. The output follows trace 2 when the input rises above the turn-on voltage threshold Vhi, and then follows trace 4 as the input falls back below the turn-off voltage threshold Vlo.
The schematic diagram of a conventional non-inverting CMOS Schmitt trigger is give in FIG. 2. It includes two P-channel field effect transistors (FETs) P1pa and P2pa which have their source-drain current circuits connected in series with the source-drain current circuits of a pair of N-channel FETs N1pa and N2pa ("pa" indicates "prior art"). The P-channel end of the series circuit is connected to a positive voltage supply line Vdd, typically 5 volts, while the N-channel end of the circuit is connected to a lower voltage reference such as ground. An input terminal 6 is connected in common to the gate control electrodes for each of the FETs. A third P-channel device P3pa has its source-drain circuit connected between ground and the junction 8 of the P1pa/P2pa current circuits, while a third N-channel device N3pa has its source-drain circuit connected between Vdd and the junction 10 of the current circuits for N-channel devices N1pa and N2pa. The gate electrodes of P3pa and N3pa are connected together to the junction 12 of the current circuits for P2pa and N1pa, which in turn is connected through an inverter INV1 to an output terminal 14.
In operation, assume that the input signal at terminal 6 is initially LO. The P-channel devices P1pa and P2pa will thus be ON, while the N-channel devices N1pa and N2pa will be OFF. This ties node 12 to a HI state equal to Vdd, which in turn holds P3pa off and N3pa on to set the node 10 HI (less a threshold voltage). The output at terminal 14 at this time is the inverted value of the signal at node 12, or LO.
Assume now that the input voltage at terminal 6 begins to rise. When the input voltage has become great enough, the N-channel devices N1pa and N2pa will become conductive, while the P-channel devices P1pa and P2pa will turn OFF. When conductive FET N2pa connects node 10 to the ground reference, which in turn grounds nodes 12 through N1pa; the result is a HI inverted signal at output terminal 14. However, N2pa has to overcome the connection of Vdd to node 10 (through N3pa) before it can place that node in a LO state. The relative sizings of N1pa, N2pa and N3pa are selected to set the threshold voltage level Vhi at which this transition to a HI output occurs. Conversely, once the trigger circuit output is HI, P3pa is held in a conductive state by virtue of its gate's ground connection through N1pa and N2pa, while P1pa and P2pa are held OFF. For the circuit output at terminal 14 to revert to a L0 state when the input signal at terminal 6 falls, P1pa must become conductive enough to overcome the grounding effects of P3pa and set node 8 at a HI level corresponding to Vdd. This is the point at which the circuit switches back to a LO output, and the relative sizes of P1pa, P2pa and P3pa are selected so that the switching transition occurs at the threshold voltage level Vlo, thus providing the proper amount of hysteresis.
While this circuit is capable of switching at the desired levels Vhi and Vlo when the circuit design is properly implemented, in practice the actual switching points have been found to be sensitive to variations in the manufacturing process, the ambient temperature and the power supply voltage. Such variations in the Vhi and Vlo values impact the voltage hysteresis and the circuit's speed, as well as its absolute switching points. One way to reduce the effects of variations in the manufacturing process is to use metal oxide semiconductor (MOS)FETs with large widths and lengths. Also, to maintain the switching speed requirements, and especially to accommodate a slow process condition, MOSFETs having large width-to-length ratios are employed. However, this requires more chip area for the transistors and increases their switching noise, especially when a fast process condition is encountered. In addition, the circuit is not readily adaptable to various Vdd power supply values. For example, if it is desired to reduce Vdd from 5 V operation down to 3 V operation, the circuit would either have to be redesigned, or a separate Schmitt trigger design for a 3 V supply would have to be provided on the same chip.
A Schmitt trigger design that improves upon the above limitations is disclosed in O'Shaughnessy et al. U.S. Pat. No. 4,859,873, assigned to Western Digital Corporation, the assignee of the present invention. In this patent, independent biased threshold sections are provided for controlling the Vhi and Vlo switching points. A drive disabling switch blocks one of the threshold sections from driving a logic node toward a predetermined logic state, with the drive disabling switch operated to obtain unidirectional sensitivity to the crossing of the threshold voltage level associated with its corresponding threshold section. While the patent represents an improvement over prior designs, it still has certain disadvantages. Among these is the inclusion of a fairly large number of devices in its switching (as opposed to bias) section. Since multiple Schmitt triggers are commonly used on the same chip (for example, an 8-bit bus will normally require eight Schmitt triggers), the provision of multiple switching sections will consume more chip area than is desirable.
Another important limitation of the patented circuit is that, although it controls the input voltage thresholds at which switching is initiated, this does not correspond exactly to the change in output states that results from a switching operation. Since a finite amount of time is required to complete a triggering operation from an OFF to an ON state, the actual input voltage will exceed the nominal Vhi by the time the circuit has actually switched ON in an effective manner; the converse applies when the circuit switches back to an OFF state. The O'Shaughnessy et al. patent also requires the use of a NOR gate in the trigger section that reduces the switching speed. Furthermore, only the input voltage level at which a switching action is initiated, not the voltage level at which effective switching takes place, adjusts to processing and voltage supply variations.
Recognizing its limitation in switching speed, the O'Shaughnessy et al. patent suggests the use of larger current mirrors to obtain larger currents and a correspondingly faster switching operation. However, larger currents generally involve larger device sizes, a higher level of AC power dissipation and an increase in transient noise.
Finally, the patented circuit employs saturated transistors with relatively large drain-source voltage drops in series with other transistors. These voltage drops may not leave enough "head room" to accommodate a drop to a lower Vdd supply, such as going from 5 to 3 volts.